Size reduction of the metal-oxide-semiconductor field-effect transistor (MOSFET) has enabled the continued improvement in speed performance, density, and cost per unit function of integrated circuits over the past few decades. As the gate length of the conventional bulk MOSFET is reduced, the interaction of the source and drain with the channel is increased resulting in gained influence on the channel potential. Consequently, a transistor with a short gate length suffers from problems related to the inability of the gate to substantially control the on/off states of the channel. Phenomena such as reduced gate control associated with transistors having short channel lengths are known as short-channel effects. Increased body doping concentration, reduced gate oxide thickness, and ultra-shallow source/drain junctions are ways to suppress short-channel effects.
When the gate length is scaled down into the sub-50 nanometer (nm) regime, the requirements for body-doping concentration, gate oxide thickness, and source/drain (S/D) doping profiles to control short-channel effects become increasingly difficult to meet when conventional device structures based on bulk silicon (Si) substrates are employed. For device scaled down well into the sub-50 nm regime, a promising approach for controlling short-channel effects is to use an alternative device structure and the surround-gate or wrap-around gate structure. The multiple-gate transistor structure is expected to extend the scalability of CMOS technology beyond the limitations of the conventional bulk MOSFET. The introduction of additional gates improves the capacitance coupling between the gates and the channel, increases the control of the channel potential by the gate, helps the suppression of short channel effects, and prolongs the scalability of the MOS transistor.
Strain-induced mobility enhancement is another approach to improve transistor performance in addition to device scaling. Significant mobility enhancement has been reported for both electrons and holes in conventional bulk transistors using silicon channel under biaxial tensile strain. It would be desirable to exploit the effects of strain-induced band structure modification to enhance carrier mobilities in multiple-gate transistors. However, there has been no research publications on the use of strained channel for enhancement of performance in multiple-gate transistors. This is because techniques used to induce the biaxial tensile strain for enhancement of carrier mobilities in conventional bulk transistors are not applicable to multiple-gate transistor structures.
A conventional technique used to induce a biaxial tensile strain in the channel region of a conventional bulk MOSFET makes use of a relaxed silicon germanium (SiGe) buffer layer, as shown in device 10 of FIG. 1A. The relaxed SiGe layer 12 which is formed on top of the graded SiGe buffer layer 14 on top of Si substrate 16 has a larger lattice constant compared to relaxed Si. A thin layer 20 of epitaxial Si grown on relaxed SiGe 12 will be under biaxial tensile strain, as shown in FIG. 1B. Both hole and electron mobilities are enhanced in the strained Si layer 20. Since a multiple gate device such as the double-gate fin FET structure resides on a silicon-on-insulator substrate and employs a fin-like channel, the conventional approach that employs a relaxed SiGe buffer is not applicable. In addition, the device structure and channel orientation of a multiple-gate transistor may be significantly different than that of the conventional bulk MOSFET. This means that the nature of strain required for enhancement of carrier mobilities in a multiple-gate device may be significantly different than that used for the conventional bulk MOSFET.
To overcome the shortcomings of the prior art, it is therefore an object of the invention to provide a multiple-gate transistor structure with a strained channel.
It is another object of the invention to illustrate the nature and direction of a useful strain required for a non-conventional multiple-gate device structure.
It is a further object of the invention to provide a method of manufacture for the strained-channel multiple-gate transistor.